ECG Monitor / Defibrillator (Class III)
Study the performance bottlenecks in product that contribute to hazardous situations. Provide recommendations to architecture changes and implementation to improve performance and recover system resources to enable the addition of device features requested by customers.
The product has been deployed around the world with a large installed base, and integrates a broad range of features after being in service over 15 years. The device software is extremely constrained by hardware resources (CPU, memory, etc.), and its code base has evolved with major inefficiencies in implementation and mis-use of the original architecture.
Moreover, the resident RTOS is out dated and does not offer robust memory management that can counter act the software complexities with extensive dynamic memory allocations causing high levels of fragmentation.
Using a suite of embedded tracing tools and performance instrumentation within the device software, the top priority use cases (including those that were traceable to hazardous situations) were carefully examined, simulating stress conditions and observing system resources and internal dynamic interactions. The analysis results revealed that the inter-communications mechanism using a publish / subscribe design pattern suffered greatly under limited hardware resources (CPU, and memory) and could not effectively handle the data production rate leading to system failure in some cases. A relatively simple design change was proposed, along with a prototype build, which replaced the publish / subscribe inter-communications with a shared memory structure. This reduced data publication rates using static memory allocations, resulting in more than 30% CPU load reduction and dynamic memory requirements, and added more than 50% safety margin to the complete software system.
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